The present invention relates to a semiconductor device, and to, for example, a semiconductor device that includes a circuit for transmitting and receiving signals between different power supplies.
Charged Device Model (CDM) is one of electrostatic discharge models in semiconductor chips. A CDM withstand voltage is evaluated by a test method in which a whole semiconductor chip is charged, and a GND (metal) terminal is brought into contact with a test pin to discharge.
In an advanced process, miniaturization promotes thinning of gate oxide films of MOS transistors, and thus a reduction in a gate withstand voltage becomes prominent. Therefore, chances in which a gate breakdown occurs in a MOS transistor (in particular, a MOS transistor that receives a different power supply crossing signal on a semiconductor chip on which analog and digital circuits are mounted and that supplies different power supplies respectively to the analog and digital circuits) at the time of testing electrostatic discharge (especially at the time of a CDM test) for evaluating Electro-Static Discharge (ESD) resistance. Hereinafter, in such a semiconductor chip, a region occupied by a digital circuit shall be referred to as a “core logic region”, and a region occupied by an analog circuit shall be referred to as an “analog IP region”.
An analog power supply that is supplied to an analog circuit inside an analog IP (Intellectual Property) region is often electrically separated from a digital power supply for the purpose of avoiding noise propagated from the digital power supply that is supplied to a digital circuit inside a core logic region. However, the separation between the digital and analog power supplies often works against ESD, especially at the time of a CDM test, due to the following factors (1) and (2).
(1) A capacitance between a power supply voltage line and a reference voltage line (a ground line) in the analog IP region is smaller than that in the core logic region.
(2) A package capacitance added to the analog IP region at the time of a CDM test is smaller than a package capacitance added to the core logic region.
This is because that a size of the analog circuit in the analog IP region is smaller than that of the digital circuit in the core logic region. As described above, in most cases, a requested size of the analog circuit is smaller than that of the digital circuit. At the time of a CDM test, most of a surge current flowing from a terminal is considered to be passed to the core logic region with a greater package capacitance, especially to the reference voltage line. At the time of a CDM test on an analog power supply terminal, as a CDM current flows from the terminal to the reference voltage line in the core logic region through a plurality of protection elements, a potential difference generated in a circuit part that transmits a different power supply crossing signal between the core logic region and the analog IP region (the circuit part is hereinafter referred to as a “different power supply crossing part”) is likely to be great, and thus a gate breakdown can easily occur. Accordingly, in such a semiconductor chip, it is desired to incorporate a mechanism that improves an ESD resistance of the different power supply crossing part, which is a weak point in the CDM test.
Japanese Unexamined Patent Application Publication No. 2006-100606 discloses a semiconductor device that can prevent electrostatic discharge events generated between a plurality of power supplies, especially electrostatic discharge events by CDM, with a small number of protection circuits. This semiconductor device includes a circuit block that operates according to a first power supply voltage and a first reference voltage and circuit block that operates according to a second power supply voltage and a second reference voltage. The semiconductor device includes a clamp circuit that clamps a potential difference between the first power supply voltage and the second reference voltage, a clamp circuit that clamps a potential difference between the second power supply voltage and the first reference voltage, and a clamp circuit that clamps a potential difference between the first reference voltage and the second reference voltage.